1. Field of the Invention
This disclosure relates to floating point addition circuits, and in particular to a leading zero/one detection circuit and method.
2. Description of the Related Art
After a floating point addition, normalization is performed on the unnormalized sum of operands so that the resulting sum is a normalized number. In conventional methods, the unnormalized sum is searched by leading zero/one detection (LZD) techniques for the leading zero/one, depending on the sign of the number. Then the unnormalized sum is shifted by the amount determined by the LZD to the left and the floating point is adjusted accordingly. Generally, the amount to be shifted cannot be calculated until the addition is done. Various LZD circuits and methods are known in the art. In another technique that significantly speeds circuit operation, U.S. Pat. No. 4,758,974 to Fields et al., which is co-assigned herewith and is incorporated by reference, describes a most significant digit (MSD) location system and method to at least approximately determine the MSD during the addition operation.